1. Field of the Invention
The present invention generally relates to the art of semiconductor memories, and more specifically to a flash or block erase electrically erasable programmable read-only memory (EEPROM) cell which is programmable at high speed, with low applied voltages and at high temperatures.
2. Description of the Related Art
A flash or block erase EEPROM semiconductor memory includes an array of cells which can be independently programmed and read. The size of each cell and thereby the memory are made small by omitting select transistors which would enable the cells to be erased independently. All of the cells are erased together as a block.
A conventional flash EEPROM is described in an article entitled "A FLASH-ERASE EEPROM CELL WITH AN ASYMMETRIC SOURCE AND DRAIN STRUCTURE", by H. Kume et al, IEDM, 25.8, 1987, pp. 560-563. Each cell includes a source and a drain which are formed on opposite sides of a channel region in a substrate. A first oxide layer, a floating gate, a second oxide layer and a control gate are formed over the channel region.
The cell is programmed by applying, typically, 12 V to the control gate, 6 V to the drain and grounding the source, which causes hot electrons to be injected from the drain depletion region into the floating gate. Upon removal of the programming voltages, the injected electrons are trapped in the floating gate and create a negative charge therein which increases the threshold voltage of the cell to a value in excess of approximately 6 V.
The cell is read by applying 5 V to the control gate and 1 V to the drain, and sensing the impedance of the cell at the source. If the cell is programmed and the threshold voltage (6 V) is higher than the control gate voltage (5 V), the control gate voltage will be insufficient to enhance the channel and the cell will appear as a high impedance. If the cell is not programmed or erased, the threshold voltage will be low, the control gate voltage will enhance the channel and the cell will appear as a low impedance.
The cell is erased by applying typically 12 V to the source, grounding the control gate and allowing the drain to float. This causes the electrons which were injected into the floating gate during programming to be removed by Fowler-Nordheim tunneling from the floating gate to the source.
A problem with the conventional flash EEPROM cell configuration is that semiconductor memories are often required to operate at high temperatures on the order of 125.degree. C. As discussed in an article entitled "A 5 VOLT HIGH DENSITY POLY-POLY ERASE FLASH EPROM CELL", by R. Kazerounian et al, IEDM 1988, pp. 436-439, hot electron injection efficiency decreases with temperature, and the length of time required to program a conventional flash EEPROM cell at 125.degree. C. is excessive for most practical applications.